Vivado中异步FIFO的实现和使用
FIFO应用：
- 1、在千兆以太网数据写入，往DDR3里面写数据时候
- 2、AD采样时钟和内部时钟不同时，需要FIFO进行转换
- 3、同频异相时也需要用FIFO进行转换
Vivado中FIFO generator的配置方法
2、 standard FIFO read mode读取时会延迟一个周期时钟，first word fall through read mode 读取时没有延时时钟周期，给使能就有数据，read latency=0。
3、
read data count表示fifo中有多少个数据了。
异步FIFO实现
具体实现代码：
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`timescale
ns /
ps
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//
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// Company:
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// Engineer:
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//
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// Create Date: 2016/08/10 14:42:33
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// Design Name:
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// Module Name: fifo_timing
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//
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module fifo_timing(
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input wire sclk,
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input wire rst_n,
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input wire r_clk,
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input wire data_v,
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input wire [
:
] data_in,
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output wire data_ov,
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output wire [
:
] data_out,
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output wire fifo_w_clk,
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output wire fifo_r_clk,
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output wire fifo_w_en,
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output wire [
:
] fifo_w_data,
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input wire fifo_full,
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output wire fifo_r_en,
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input wire [
:
] fifo_r_data,
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input wire fifo_empty,
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input wire [
:
] fifo_rd_count
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);
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wire full;
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wire
empty;
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// r_clk
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reg r_flag;
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wire [
:
] rd_data_count;
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reg [
:
] r_cnt;
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wire rd_en;
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assign fifo_w_clk = sclk;
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assign fifo_r_clk = r_clk;
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assign fifo_w_en = data_v & (~fifo_full);
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assign fifo_w_data = data_in;
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assign fifo_r_en = r_flag & (~fifo_empty);
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assign data_out = fifo_r_data;
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assign data_ov = r_flag;
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assign rd_en = r_flag;
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always @(posedge r_clk
or negedge rst_n)
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if(rst_n ==
'b0)
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r_flag <= 1'b0;
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else
if(r_flag ==
'b1 && r_cnt == 'd255 )
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r_flag <=
'b0;
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else if(fifo_rd_count >= 'd255 && r_flag ==
'b0)
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r_flag <= 1'b1;
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always @(posedge r_clk
or negedge rst_n)
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if(rst_n ==
'b0)
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r_cnt <='d0;
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else
if(r_flag ==
'b1)
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r_cnt <= r_cnt + 1'b1;
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else
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r_cnt <=
'd0;
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assign data_ov = r_flag;
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endmodule